1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, in particular, to methods of forming integrated circuits wherein material layers having an intrinsic stress are deposited and to semiconductor processing tools that are employed in such methods.
2. Description of the Related Art
Integrated circuits include a number of individual circuit elements such as, for example, transistors, capacitors, diodes and resistors, which are interconnected by means of electrically conductive metal lines formed in an interlayer dielectric. The electrically conductive metal lines may be provided in a plurality of interconnect layers that are stacked on top of each other above a substrate. Metal lines in different interconnect layers may be electrically connected with each other by means of contact vias that are filled with metal. In and on the substrate, field effect transistors and, optionally, other circuit elements, such as capacitors, diodes and resistors, may be formed. Contact holes filled with an electrically conductive metal may be used for connecting the circuit elements with electrically conductive metal lines.
The electrically conductive metal lines may be formed in a back-end-of-line phase of semiconductor manufacturing. For forming the electrically conductive metal lines, damascene techniques may be employed. In damascene techniques, trenches and contact vias are formed in an interlayer dielectric, which may include silicon dioxide, a low-k material having a smaller dielectric constant than silicon dioxide, for example, a dielectric constant smaller than about 3.9 and/or an ultra-low-k material, which may have a dielectric constant smaller than about 2.4. In the trenches and contact vias, a diffusion barrier layer may be formed. After the formation of the diffusion barrier layer, the trenches and contact vias may be filled with a metal such as copper or a copper alloy. This may be done by means of electroplating for depositing the metal and chemical mechanical polishing for removing portions of the metal deposited outside the trenches and contact vias.
In the deposition of interlayer dielectrics over a semiconductor structure, a formation of an intrinsic stress in the deposited material may occur. In semiconductor structures wherein the interlayer dielectric includes a relatively soft material, which may be the case, in particular, when the interlayer dielectric includes an ultra-low-k material, an intrinsic stress of the interlayer dielectric may increase the risk of a formation of cracks in the interlayer dielectric. Cracks may be formed during the manufacturing of a semiconductor structure and/or during the operational life of the semiconductor structure, leading to yield loss or reliability failures. The formation of cracks may be driven by an adhesion between interconnect layers, an overall stress state of the stack of interconnect layers and/or local stress gradients.
In view of the situation described above, the present disclosure provides methods and semiconductor processing tools which may help to substantially avoid or at least reduce the occurrence of issues as described above.